1. Field of the Invention
The present invention relates to a clock recovery circuit for extracting a clock from inputted data, and more particularly to an oversampling clock recovery circuit for sampling transmitted data with a plurality of clocks that are out of phase with each other.
2. Description of the Related Art
In recent years, there has been proposed a high-speed protocol for the transmission of data. In view of the proposed high-speed protocol, there are demands for high-speed clock recovery circuits for extracting a clock from data transmitted at a high rate, or high-speed phase-locked loops (PLL) for synchronizing the frequency of a clock used within a circuit with the frequency of a clock transmitted to the circuit.
One conventional analog clock recovery circuit uses a single-phase clock whose each positive-going edge is associated with one-bit data for phase comparison. According to the conventional analog clock recovery circuit, since the data rate and the clock frequency need to be equal to each other, if the data rate is at a Gbps level, then it is necessary that the clock frequency be a high frequency at a GHz level. It has been difficult to meet demands for high-speed clock recovery circuits and high-speed phase-locked loops. For example, it is not easy to increase the oscillation frequency of a voltage-controlled oscillator (VCO) included in a phase-locked loop to a high frequency at a GHz level.
In order to meet the above demands, there has been proposed an oversampling clock recovery circuit for sampling transmitted data with a plurality of clocks that are out of phase with each other which have a frequency lower than the rate of data generated within the circuit. The proposed oversampling clock recovery circuit associates a plurality of positive-going edges of the clocks with one-bit data for phase comparison. The oversampling clock recovery circuit can meet the demands for high-speed clock recovery circuits because it uses clocks having a frequency lower than the data rate.
For oversampling data at twice the sampling rate with a clock frequency that is one-half of the data rate, as shown in FIG. 1A of the accompanying drawings, four-phase clocks CLK1 through CLK4 are used. For oversampling data at twice the sampling rate with a clock frequency that is one-eighth of the data rate, as shown in FIG. 1B of the accompanying drawings, 16-phase clocks CLK1 through CLK16 are used.
In the oversampling clock recovery circuit, a voltage-controlled oscillator generates a predetermined number of clocks (hereinafter referred to as xe2x80x9cmultiphase clocksxe2x80x9d) required for phase comparison, as disclosed in Japanese laid-open patent publication No. 10-4349 and U.S. Pat. No. 5,694,062.
An oversampling clock recovery circuit in which multiphase clocks are generated by a voltage-controlled oscillator will be described below with reference to FIG. 2 of the accompanying drawings. FIG. 2 is a block diagram of conventional oversampling clock recovery circuit 40, which performs phase comparison using 16-phase clocks.
In conventional oversampling clock recovery circuit 40, voltage-controlled oscillator 41 includes voltage-controlled delay line 42 comprising a cascaded array of eight differential buffers, and generates 16-phase clocks (differential 8 clock phases) while performing frequency and phase modulation.
Signal processor 13 is supplied with the 16-phase clocks from voltage-controlled oscillator 41 and extracts clocks for an oversampling process. Signal processor 13 has eight phase detectors PD2 each for carrying out phase comparison between successive three-phase clocks of the 16-phase clocks and inputted serial data. If the clocks lag the inputted serial data, then each of phase detectors PD2 outputs an UP signal. If the clocks lead the inputted serial data, then each of phase detectors PD2 outputs a DOWN signal. Based the UP signal or DOWN signal (phase difference information), signal processor 13 generates control voltage V4 suitable for bringing the clocks into phase with the inputted serial data, and applies generated control voltage V4 to voltage-controlled oscillator 41. Thus, voltage-controlled oscillator 41 is feedback-controlled to modulate the frequency and phase of the clocks again based on control voltage V4 in order to bring the clocks into phase with the inputted serial data, thus generating 16-phase clocks that are supplied to signal processor 13. In FIG. 2, control voltage V4 is generated by signal processing circuit 15, charge pump CP2, and low-pass filter LPF2, for example. Signal processing circuit 15 comprises a majority circuit, an averaging circuit, etc.
Converters CV1 converts the multiphase clocks from a differential signal into a single-phase signal and also converts them from a small amplitude to a large amplitude before the multiphase clocks are supplied to signal processor 13.
If clock recovery circuit 40 is supplied with 2.5 Gbps serial data, then clock recovery circuit 40 uses a clock frequency of 312.5 MHz (a period of 3200 ps), and each of the differential buffers of voltage control delay line 42 has a propagation delay time of 200 ps. Therefore, clock recovery circuit 40 generates 16-phase clocks that are successively out of phase by 200 ps.
The conventional clock recovery circuit has suffered the following problems:
In the conventional clock recovery circuit, the voltage-controlled oscillator is controlled to achieve phase synchronization. Therefore, in the process of phase control, the frequency is necessarily caused to fluctuate, making jitter characteristics poor and lowering the quality of the clocks.
The conventional clock recovery circuit also suffers a problem when applied to a transceiver having a number of serial input/output channels.
For example, if conventional clock recovery circuits 40 are provided in respective channels as shown in FIG. 3 of the accompanying drawings, then a number of voltage-controlled oscillators 41 are present on an IC chip. Voltage-controlled oscillators 41 on the IC chip tend to resonate between the channels, making jitter characteristics poor and lowering the quality of the multiphase clocks. Furthermore, since the voltage-controlled oscillators generally have a large power consumption requirement, the overall chip consumes a large amount of electric energy.
If one voltage-controlled oscillator is shared by a number of channels to supply multiphase clocks to the channels, then difficulty arises in supplying the multiphase clocks to the channels. In the process of supplying the multiphase clocks to the channels, the multiphase clocks are degraded to different extents for the different phases, resulting in a reduction in the quality of the multiphase clocks. An arrangement wherein one voltage-controlled oscillator is shared by a number of channels to supply multiphase clocks to the channels will be described below with reference to FIG. 4 of the accompanying drawings.
As shown in FIG. 4, channels ch1 through ch(n) are associated respectively with oversampling clock recovery circuits 60(1) through 60(n) each having signal processor 13 and phase control circuit 11. Single phase-locked loop 50 including voltage-controlled oscillator 51 generates multiphase clocks (16-phase clocks in FIG. 4) and supplies the generated multiphase clocks to respective oversampling clock recovery circuits 60(1) through 60(n). Channels ch1 through ch(n) are not associated with respective voltage-controlled oscillators, but receive the multiphase clocks from phase-locked loop 50 and performs phase control between the multiphase clocks and inputted data.
Since the single voltage-controlled oscillator is shared by the many channels, the system shown in FIG. 4 is free of drawbacks that would be caused if a number of voltage-controlled oscillators were present on one IC chip.
However, since phase-locked loop 50 is required to supply multiphase clocks to many channels ch1 through ch(n), it suffers some difficulty in distributing the clocks. For example, the distribution of the 16-phase clocks to a wide range of circuits is liable to increase electric power consumption needed for buffering. Therefore, the efficiency of clock distribution from phase-locked loop 50 to the channels is poor.
It is highly difficult to distribute the 16-phase clocks to clock recovery circuits 60 of the respective channels while keeping the 16-phase clocks accurately out of phase with each other, i.e., while keeping the phase differences accurately between the 16-phase clocks. Accordingly, the problem of the reduced quality of the multiphase clocks cannot be solved.
Furthermore, as shown in FIG. 4, each of clock recovery circuits 60 of respective channels ch1 through ch(n) needs phase control circuits 11 for performing phase comparison between the multiphase clocks and the inputted data and subsequently phase synchronization between the inputted data and the clocks. If the 16-phase clocks are received and synchronized in phase with the inputted data, as shown in FIG. 4, each of channels ch1 through ch(n) requires eight phase control circuits 11. Inasmuch as phase control circuits 11 are highly critical in their functions and generally need a large circuit scale and a large amount of electric power to be consumed, it is not preferable to provide 8 functionally identical phase control circuits per channel.
It is therefore an object of the present invention to provide an oversampling clock recovery circuit which has a plurality of phase comparators for sampling inputted data with a plurality of clocks out of phase with each other for phase comparison, for controlling the phase of the clocks based on phase difference information output from the phase comparators, the oversampling clock recovery circuit being capable of preventing jitter characteristics thereof from being lowered and of generating high-quality clocks.
Another object of the present invention is to provide an oversampling clock recovery circuit which is capable of generating high-quality clocks when applied to a transceiver having a number of serial input/output channels.
Still another object of the present invention is to provide an oversampling clock recovery circuit which has a high circuit area efficiency, a high electric power efficiency, and a high clock distribution efficiency when applied to multiple channels.
To achieve the above objects, there is provided in accordance with a first aspect of the present invention an oversampling clock recovery circuit having a plurality of phase comparators for sampling inputted data with a number of clocks which are out of phase with each other for phase comparison, for controlling the phase of the clocks based on phase difference information output from the phase comparators, comprising a phase control circuit for being supplied with a fewer clocks than the number of clocks and controlling the phase of the supplied clocks, and a delay-locked loop for generating the number of clocks based on the fewer clocks controlled in phase by the phase control circuit, and supplying the generated number of clocks to the phase comparators, the arrangement being such that a phase control signal based on the phase difference information output from the phase comparators is supplied via a feedback loop to the phase control circuit.
With an oversampling clock recovery circuit according to the first aspect, a relatively small number of clocks are supplied, and controlled in phase by a phase control circuit. From the phase-controlled clocks, a delay-locked loop (DLL) generates a relatively large number of clocks (multiphase clocks) required for phase comparison, and supplies generated clocks to the phase comparators for phase comparison.
The oversampling clock recovery circuit according to the first aspect offers the following advantages:
First, since no voltage-controlled oscillator is required in each channel, jitter characteristics are not degraded by frequency fluctuations.
Secondly, even though the oversampling clock recovery circuit is provided in each channel, no voltage-controlled oscillator is included in each channel, and hence there is no possibility of undue interference such as clock resonance between the channels.
Thirdly, even though oversampling clock recovery circuit 10 is provided in each channel, it is not necessary to distribute multiphase clocks to each channel, but a relatively small number of clocks may be distributed to each channel. Therefore, no unduly large increase in the consumption of electric power is needed for the distribution of multiphase clocks.
According to the fourth advantage, even though the oversampling clock recovery circuit is provided in each channel, it is not necessary to distribute multiphase clocks to each channel, but a relatively small number of clocks may be distributed to each channel. Therefore, the system is free of a reduction in the quality of multiphase clocks when the clocks are distributed, due to variations or skews of phase intervals between the multiphase clocks.
The fifth advantage is that since the phase is controlled with respect to a relatively small number of clocks. Therefore, the circuit scale and the power consumption can be made smaller than the conventional arrangement which controls the phase of multiphase clocks.
The sixth advantage is that because a relatively small number of clocks which have been controlled highly accurately in phase by the phase control circuit are developed into multiphase clocks by the delay-locked loop immediately prior to phase comparison, it is possible to supply the phase comparators with extremely high-quality multiphase clocks that are kept out of phase accurately.
According to the seventh advantage, since only one phase control circuit is used that is required to operate highly critically, the recovery process is made much more reliable than the conventional arrangement which comprises a plurality of parallel phase control circuits.
According to a second aspect of the present invention, in the oversampling clock recovery circuit according to the first aspect, the fewer clocks comprise one or two clocks.
According to a third aspect of the present invention, in the oversampling clock recovery circuit according to the first aspect, the fewer clocks comprise one clock.
With the oversampling clock recovery circuit according to the third aspect, a single-phase clock is supplied, and controlled in phase by a phase control circuit. From the single-phase clock, a delay-locked loop generates a relatively large number of clocks (multiphase clocks) required for phase comparison, and supplies generated clocks to the phase comparators for phase comparison.
Since a voltage-controlled oscillator (VCO) or a phase-locked loop (PLL) is a source for supplying clocks of an accurate frequency, they should preferably be of a differential arrangement having good jitter characteristics.
In the oversampling clock recovery circuit according to the third aspect, since the phase control circuit and the delay-locked loop are of a single-phase arrangement, the oversampling clock recovery circuit has a low power requirement while its jitter characteristics are not degraded
The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate examples of the present invention.